Modern metal-oxide-semiconductor (MOS) integrated circuit (IC) fabrication technology is capable of producing very fast transistors (e.g., several gigahertz and above). However, an undesirable side effect of these fast transistors is that they characteristically exhibit a non-negligible leakage current when they are otherwise supposed to be turned off due, at least in part, to sub-threshold effects. In portable devices, as well as other devices in which power consumption is critical, such as, for example, cell phones, laptop computers, personal digital assistants (PDAs), etc., this leakage current can significantly shorten the useful battery life of the device.
It is well known to employ circuitry which runs on two or more different voltage levels in order to reduce overall power consumption in an IC device. For instance, circuitry utilized with many portable devices may be configured so that a portion of the circuitry, such as, for example, input/output (IO) buffers, runs at a higher voltage level (e.g., about 3.3 volts), as may be supplied by an IO voltage source, while another portion of the circuitry, such as, for example, core logic, runs at a substantially lower voltage level (e.g., about 1.0 volt), as may be supplied by a core voltage source. While using multiple power domains in an IC may reduce power consumption therein, this arrangement does not reduce leakage current.
In order to reduce leakage current in an IC having multiple power domains, one or more of the power domains that are not needed at a given time may be left unconnected during at least part of the normal circuit operation. However, this approach can pose a substantial reliability risk, since the unconnected power domain on the IC may float to a voltage level high enough to damage MOS devices connected thereto. Although the unconnected power domain can be forced to ground, doing so would require changes to the printed circuit board configuration, which can be costly. Additionally, forcing the power domain to ground would increase the risk of latch-up in the IC, since N-tubs (in which p-channel MOS transistors may be formed) which are normally connected to the power domain would be connected to ground, thereby undesirably allowing a PN junction between the N-tub and substrate to become forward-biased.
Accordingly, there exists a need for reducing leakage current in an IC having multiple power domains that does not suffer from one or more of the above-noted problems exhibited by conventional ICs.